1. Field of the Invention
This disclosure relates to a nonvolatile memory device, and more particularly, to a NOR flash memory device with multi level cell and a read method thereof.
2. Description of the Related Art
A nonvolatile memory device can retain data stored in memory cells even when power is removed. Examples of the nonvolatile memory device are programmable read only memory (PROM), erasable PROM (EPROM), electrically eraseble EPROM (EEPROM), flash memory, and so on. The flash memory devices are classified into NAND flash memory device and NOR flash memory device. Because the NOR flash memory device has higher speed than the NAND flash memory, it is widely used in mobile terminals that necessarily require high-speed data processing.
The NOR flash memory device includes memory cells connected between bit lines and source lines. Memory cells connected to one word line are commonly connected to one source line.
Each of the memory cells is sensed as an on cell or an off cell according to a word line voltage. The on cell means that the memory cell is in a turned-on state because a word line voltage is higher than a threshold voltage. In this state, more than a predetermined amount of a current flows through the memory device. The off cell means that the memory cell is in a turned-off state because a word line voltage is lower than a threshold voltage. In this state, no current or less than a predetermined amount of a current flows through the memory device.
Generally, it is preferable that a semiconductor memory device has a large storage capacity in a small area. In order for the NOR flash memory to have a large storage capacity in a small area, the degree of integration has to be increased. The existing semiconductor fabrication technologies, however, have a limitation in increasing the degree of integration. Hence, methods of increasing the storage capacity in the same degree of integration have been developed.
One of these methods is to store multi-bit data in one memory cell. A memory cell that can store multi-bit data is called a multi level cell (MLC) or multi-bit cell. For example, an MLC may have four states “11”, “10”, “01” and “00” depending on its threshold voltages. Because the MLC can store 2-bit data in one memory cell, it has two times the storage capacity of a single level cell (SLC).
There are several methods of reading the states of the MLC. One of these methods is to read the states of the memory cell while increasing a word line voltage. For example, if the memory cell is an on cell for the first word line voltage WL_L, the memory cell is in a state “11”. If the memory cell is an off cell for the first word line voltage WL_L and an on cell for the second word line voltage WL_M, the memory cell is in a state “10”. If the memory cell is an off cell for the second word line voltage WL_M and an on cell for the third word line voltage WL_H higher than the second word line voltage WL_M, the memory cell is in a state “01”. If the memory cell is an off cell for the third word line voltage WL_H, the memory cell is in a state “00”.
During a read operation performed on the memory cell while increasing the word line voltage, the memory cell sensed once as the on cell is again sensed as the on cell even though the word line voltage increases. For example, after the first word line voltage WL_L is applied to the memory cell, if the sensing result is that the memory cell is the on cell, the memory cell is again sensed as the on cell when the second or third word line voltage WL_M or WL_H is applied. Accordingly, once the memory cell is sensed as the on cell in the first sensing operation, the second or third sensing operation is unnecessary.
In the case of the conventional NOR flash memory device, however, if the memory cell is determined as the on cell in the first sensing operation, a current flows through the memory cell in the second or third sensing operation, resulting in the unnecessary current consumption. In addition, because a current flows through the memory cell in the second or third sensing operation, a voltage level of the source line increases so that the second or third operation may be unstable. That is, although the memory cell of a state “10” has to be sensed as the on cell in the second sensing operation, the memory cell may be sensed as the off cell because the source line voltage increases from the additional current.